PHASE LOCKED LOOP SYNTHESIOR ËøÏà»·
BLOCK DIAGRAM
TYPICAL PERFORMANCE
Frequency Range: 0.1~10GHz
Band: Exceed Double Jump Time: >30uS
Control: Serial / Parallel Frequency Stability: ¡À1¡Á10-7/Day
Spurious Rejection: >60dBc
Harmonic Rejection: >50dBc
Single Band Phase Noise: -85dBc/Hz@1KHz (@8GHz)
Output Power: >13dBm
Power ripple: ¡À1dB
VSWR: <1.5
Step: 1MHz (Up to 1KHz)
Operation Temperature: -40¡æ~+85¡æ
Outline Drawing: TBD |